Register–memory architecture
In computer engineering, a register–memory architecture is an instruction set architecture that allows operations to be performed on (or from) memory, as well as registers.[1] If the architecture allows all operands to be in memory or in registers, or in combinations, it is called a "register plus memory" architecture.[1]
In a register–memory approach one of the operands for operations such as the ADD operation may be in memory, while the other is in a register. This differs from a load–store architecture (used by RISC designs such as MIPS) in which both operands for an ADD operation must be in registers before the ADD.[1]
Example of Load-Store (RISC)
;Add mem1 to mem2 mov r1, [mem1] ; Load first value into register mov r2, [mem2] ; Load second value into register add r2, r1, r2 ; r2 = r1 + r2 mov [mem2],r2 ; Store result
Example of register-memory (CISC)
Some register-memory machines cannot write ALU results to memory, only their registers. This is like an accumulator machine with multiple accumulators:
;Add mem1 to mem2, if add-register-to-memory instructions are not supported mov r1, [mem1] ; Load first value into register add r1, [mem2] ; Add second value into register mov [mem2], r1 ; Store result
Some register-memory machines are able to write ALU results directly to memory, saving an instruction:
;Add mem1 to mem2, if add-register-to-memory instructions are supported mov r1, [mem1] ; Load first value into register add [mem2],r1 ; Add it to second value
Example of register plus memory (CISC)
;Add mem1 to mem2 add [mem2],[mem1] ; Add first to second value
An example of register-memory architecture that can write ALU results to memory is the Intel x86.[1]
Examples of register plus memory architecture are:
- IBM System/360 and its successors, which support memory-to-memory fixed-point decimal arithmetic operations, but not binary integer or floating-point arithmetic operations;[2][3][4]
- PDP-11, which supports memory (or register) source and destination operands for most two-operand integer operations;[5]
- VAX, which supports memory or (or register) source and destination operands for binary integer and floating-point arithmetic;[6]
- Texas Instruments MSP430 is a rare microcontroller that supports memory (or register) source and destination operands for all 24 of its two-operand operations.[7]
- Motorola 68000 series can move data memory-to-memory with nearly all addressing modes. All other integer arithmetic/logic operations require at least one parameter to reside in a register, making it primarily a register-memory machine.[8]
See also
References
- ^ a b c d Michael J. Flynn (1995). Computer architecture: pipelined and parallel processor design. Jones & Bartlett Learning. pp. 9–12. ISBN 0867202041.
- ^ IBM System/360 Principles of Operation (PDF). IBM. September 1968. A22-6821-7.
- ^ IBM Enterprise Systems Architecture/370 Principles of Operation (PDF). IBM. August 1988. SA22-7200-0.
- ^ z/Architecture Principles of Operation (PDF). IBM. September 2017. SA22-7832-11.
- ^ pdp11 processor handbook pdp11/04/34a/44/60/70 (PDF). DEC. 1979. Retrieved 26 September 2025.
- ^ VAX Architecture Reference Manual (PDF). Digital Equipment Corporation. 1987. EY-3459E-DP.
- ^ "MSP430F552x, MSP430F551x Mixed-Signal Microcontrollers" (PDF). Texas Instruments. Retrieved 10 November 2025.
- ^ MC68020 32-Bit Microprocessor User's Manual (PDF). Motorola. 1984. MC68020UM[ADI).